Flash memory is a form of non-volatile computer memory that can be electrically erased and reprogrammed. Flash memory is erased and programmed in blocks comprising multiple locations. Flash memory is widely used wherever a significant amount of non-volatile, solid-state storage is needed. Conventional flash memory applications include digital audio players, digital cameras and mobile phones. Flash memory is also used in USB flash drives (thumb drives), which are used for general storage and transfer of data between computers. It is also used in video game consoles to store game save data.
SmartMedia™ is a memory card standard using flash memory, developed by Toshiba Corporation. Typically, a SmartMedia™ card is used as storage media for a portable device, in a form that can easily be removed for access by a PC.
When compared to a hard disk drive, a limitation of flash memory is that flash memory has a finite number of erase-write cycles (most commercially available flash products are guaranteed to withstand one hundred thousand programming cycles) so that care has to be taken when moving traditionally hard-drive based applications, such as operating systems, to flash-memory based devices such as CompactFlash. This effect is partially offset by some chip firmware or filesystem drivers by counting the writes and dynamically remapping the blocks in order to spread the write operations between the sectors, or by write verification and remapping to spare sectors in case of write failure.
Low-level access to a physical flash memory by device driver software is different from accessing common memories. Whereas a common RAM will simply respond to read and write operations by returning the contents or altering them immediately, flash memories need special considerations, especially when used as program memory akin to a read-only memory (ROM).
One limitation of conventional NOR flash memory is that although it can be read or programmed a byte or a word at a time in a random access fashion, it must be erased a “block” at a time. Starting with a freshly erased block, any byte within that block can be programmed. However, once a byte has been programmed, it cannot be changed again until the entire block is erased. NOR flash memory offers random-access read and programming operations, but cannot offer random-access rewrite or erase operations.
In NAND flash memory reading data can not be performed on individual addresses. Reading, erasing and writing operations are performed block-wise on all NAND flash memories. NAND flash memory is conventionally organized in zones of 1024 blocks. In each zone, 1000 blocks are used for data storage, and 24 are reserved against bad NAND blocks. This memory organization scheme originated with the SmartMedia™ specification. Manufacturers of NAND memories typically guarantee only 1000 out of 1024 good blocks over the life of the NAND.
One block is equal to one Megabit, or one million bits. This is 128 KiloBytes (KB). One zone is 1024 blocks, so is 128 MegaBytes (MB). For example, a 1 GigaByte (GB) Flash drive would have 8 zones of memory. The purpose of having zones is to allow leeway for partial block copies, and to allow for bad blocks. Zones work in the following manner. To write new data into the middle of a block, an erased block is selected from the pool of good erased blocks. The front portion (if any) of the old block is copied into the new block, then the overwritten portion is written to the new block, then the remaining portion of the old block is copied to the new block. When all of the data has been replaced or copied, then the old block is erased.
When reading data from and writing data to a conventional flash memory, there is a performance penalty for crossing a zone boundary because the logical to physical table must be reloaded. If the flash memory is being used as a disk drive, this penalty is minimal because most disk drive accesses are sequential or linear. This means that the probability of a zone transition is much lower than if the accesses were random.
New applications such as ReadyBoost use flash memory as a cache memory which causes more zone boundary crossings. ReadyBoost is a software standard designed by Microsoft, which makes PCs running Windows Vista more responsive by using flash memory on a USB drive (USB 2.0 only), secure digital (SD) Card, Compact Flash, or other form of flash memory as a disk cache to boost system performance. When such a device is plugged in, the Microsoft Windows Autoplay dialog offers an additional option to use it to speed up the system, an additional “Memory” tab is added to the drive's properties dialog where the amount of space to be used can be configured.
FIG. 1 shows a first conventional computer system 100 using an external memory as a disk cache. The system 100 comprises a hard disk drive 110, and a bus 120 coupling the hard disk drive 110 to a motherboard bridge chip 130. The motherboard bridge chip may be a northbridge chip, or a southbridge chip, or another type of combination bridge chip.
A northbridge, also known as the Memory Controller Hub (MCH), is traditionally one of the two chips in the core logic chipset on a PC motherboard, the other being the Southbridge. Separating the chipset into Northbridge and Southbridge is common, although in some conventional solutions these two chips have been combined onto one die when design complexity and fabrication processes permit it. The northbridge typically handles communications between the central processing unit (CPU), random access memory (RAM), advanced graphics protocol (AGP) or peripheral component interconnect express (PCI-X), and the southbridge. Some northbridges also contain integrated video controllers, which are also known as a graphics and memory controller hub (GMCH).
A southbridge, also known as the input/output (I/O) controller hub (ICH), is a chip that implements the “slower” capabilities of the motherboard in a northbridge/southbridge chipset computer architecture. The southbridge can usually be distinguished from the northbridge by not being directly connected to the CPU. Rather, the northbridge ties the southbridge to the CPU.
The bridge chip 130 is coupled via bus 140 to a universal serial bus (USB) controller 150. In one embodiment, the controller 150 is a USB host controller. The controller 150 is coupled by USB bus 160 to a USB memory device 170 (often referred to as a ‘flash drive’ or ‘thumb drive’). USB flash drives are usually NAND-type flash memory data storage devices integrated with a USB interface. They are typically small, lightweight, removable and rewritable. Memory capacity typically ranges from 8 megabytes up to 64 gigabytes, limited only by flash memory densities.
In the conventional system 100, if the bridge chip 130 (driven by the central processing unit) attempts to use the conventional USB memory device 170 as a disk cache memory, the cache memory accesses are random in fashion (unlike the linear accesses of regular flash memory storage, used like a disk drive). The random accesses are likely to result in page faults, reducing system throughput and performance.
The effect of this is similar to fragmentation of a personal computer hard drive. When files are fragmented on a hard drive, file access is no longer linear. Fragmented file access is much slower than linear access, since the disk must now rotate further and move the head more to access the dispersed sectors.
FIG. 2 shoes a conventional system 200 comprising a hard disk drive 210, and a bus 220 coupling the hard disk drive 210 to a motherboard bridge chip 230. The motherboard bridge chip 230 incorporates a USB host controller 240 in the same chip/package as bridge 230. The USB controller 240 is coupled by USB bus 250 to a USB memory device 270 (often referred to as a ‘flash drive’ or ‘thumb drive’).
The conventional system 200 suffers from the same problem of random access when using the USB memory as a cache, since random access to the device produces a page fault probability determined by the number of zones less the number of logical to physical tables in the ram, divided by the number of zones. This can be expressed as:
                              numberOfZones          -                      12            ⁢                                                  ⁢            pTablesInRAM                          numberOfZones                            Eq        ⁢        .1            
For a typical 1 GByte design with 8 zones and one logical to physical table stored in RAM, 87.5% of random accesses result in a reload of the 1024 entry logical to physical table.
It would be desirable to have a solution allowing use of portable memory devices for disk cache memory.